1. Field of the Invention
The present invention relates to a semiconductor device, and a method of manufacturing the same. In particular, the present invention relates to a semiconductor device including a non-volatile memory cell isolated by a shallow trench isolation (STI) region, and a method of manufacturing the same. For example, the present invention is applicable to a non-volatile semiconductor memory device such as a NAND flash memory, and a method of manufacturing the same.
2. Description of the Related Art
In a semiconductor device, for example, non-volatile memory cell, a shallow trench isolation (STI) region is formed in a semiconductor substrate to isolate a micro memory cell (cell transistor) included in a memory cell array. The non-volatile memory having the STI structure has a need to take the following problems into consideration. Specifically, if an impurity concentration of a well region in which a memory cell is formed is low, the memory cell will easily be broken down in the following cases, and as a result, becomes failure. One is the case where a breakdown voltage against punch through between adjacent memory cells is low. Another is the case where a breakdown voltage against field inversion is low when high voltage is applied to the gate of a cell transistor. In order to increase the punch through breakdown voltage and field inversion breakdown voltage, a following method has been proposed. According to the method, the depth of a trench of the STI region is made deep, or the impurity concentration of a well region is made high. However, the method of making the depth of the trench of the STI region deep has a following problem. That is, it is difficult to sufficiently make the trench deep because the etching condition is restricted with scale-down of device region and isolation region. On the other hand, according to the method of increasing the impurity concentration of the well region, the back-bias characteristic of a transistor is degraded, and as a result, the impurity concentration of the well region cannot not be sufficiently increased.
If the width of the STI region is large, there has been proposed a following method. According to the method, a portion of the STI region is opened by photolithography, and thereafter, impurities are introduced into a portion of a semiconductor substrate under the portion of the STI region to form a punch through restricting region (field stopper region). However, this method has a following problem. For example, in a NAND flash memory having a large capacity, the width of the STI region between cell transistors connected in series in a memory cell array is very small. It is difficult to form an opening smaller than the STI region at a desired position of such a small-size STI region. The opening formed is generally undesirably displaced from the predetermined position, and thus, the distance between the punch through stopper region and device region are too close from each other, resulting in degradation of the device characteristic.
Incidentally, the following technique has been disclosed in forming DRAM (Dynamic Random Access Memory) or SRAM (Static Random Access Memory). According to the technique, a STI trench is formed using etching, and then, a silicon oxide film is formed on the side wall of the STI trench. A silicon nitride film is deposited on the silicon oxide film. Thereafter, an opening is formed in the bottom portion of the STI trench. Impurity ions are implanted through an opening of the STI trench into a portion of a semiconductor substrate to form a punch through stopper region. Thereafter, the STI trench is filled with a silicon oxide film to form a STI region. See JPN. PAT. APPLN. KOKAI Publication No. 11-340461.